Optimization of instruction fetch mechanisms for high issue rates”,in ISCA22

Recent supers calar processors issue four tnstructzons per cycle. These processors are also powered by highly-parallel supers calar cores. The potential per-formance can only be explotted when fed by high in-struction bandwidth. This task is the responsibility of the instruction fetch unit. Accurate branch prediction and low I-cache miss ratios are essential for the e@-cient operation of the fetch unit. Several studies on cache design and branch prediction address thas prob-lem. However, these techniques are not sufficient. Even in the presence of efictent cache designs and branch prediction, the fetch unit must continuously extract multiple, non-sequential instructions from the instruction cache, realign these in the proper order, and supply them to the decoder. This paper explores solutions to this problem and presents several schemes with varying degrees of performance and cost. The most-general scheme, the collapsing bufler, achieves near-perfect performance and consistently altgns in-structions in excess of 90 % of the time, over a wide range of tssue rates. The performance boost provided by compiler optimization techniques M also investi-gated. Results show that compiler optimization can significantly enhance performance across all schemes. The collapsing buffer supplemented by compder tech-niques remains the best-performing mechanism. The paper closes wtth recommendations and suggestions for future. Permission to copy without fee all or part of this material is granted provided that the copies are not made or distributed for direct commercial advantage, the ACM copyright notice and the title of the publication and its date appear, and notice is given that copyin is by permission of the Association of Computin